The present technique relates to a logic circuit including a plurality of master-slave flip-flop circuits.
A scan shift operation for an LSI test is performed using a master-slave flip-flop circuit including a master latch and a slave latch. As a sequential circuit in a logic circuit, a master-slave flip-flop circuit is generally used.
In the scan shift operation, a clock for controlling a master and a clock for controlling a slave are alternately turned on, and scan data supplied from the outside of LSI is input from a scan-in (SI) input terminal of the flip-flop circuit. The scan data output from a scan-out (SO) output terminal of the flip-flop circuit is input to an SI input terminal of another flip-flop circuit. This input operation is repeated to form a scan chain. An output of a final connected flip-flop circuit is output to the outside of the LSI. This output is measured to determine whether or not the LSI has a failure.
As the circuit scale of the LSI increases, the number of flip-flop circuits forming a scan chain also increases, resulting in an increase in power consumption of the scan chain.
Japanese Laid-open Patent Publication Nos. 07-198787 and 2000-214223 are examples-of related art.